Import the RTL Design

Import the RTL Design 


Step - 1: Now import your RTL code in a sequence of top module file is followed by the rest of the design files. For purpose of clear explanation here we are using a standard AES design. It is designed using verilog and whose topmodule name is "aes_cipher_top". AES design contains the following verilog files.

aes_cipher_top.v (Top Module)
aes_sbox.v
aes_rcon.v
aes_key_expand_128.v

Step - 2: "import rtl" reads the RTL files. To analyze RTL code use "-analyze" at the end. "-analyze" is optional command.

mantle[0]:> import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v aes_key_expand_128.v

mantle[0]:>import rtl aes_cipher_top.v  aes_sbox.v aes_rcon.v aes_key_expand_128.v MSG-10   While running 'import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v          aes_key_expand_128.v': RTL-3    Building model aes_cipher_top(aes_cipher_top) RTL-3    Building model aes_key_expand_128(aes_key_expand_128) RTL-3    Building model aes_sbox(aes_sbox) RTL-3    Building model aes_rcon(aes_rcon) /work/aes_cipher_top/aes_cipher_top

Step - 3: "set m" set the variable for the top level Design. In this design the top level model is "/work/aes_cipher_top/aes_cipher_top". The top level model path is displayed at the end of the report of the "import rtl" command.

mantle[0]:>set m /work/aes_cipher_top/aes_cipher_top

mantle[4]:>set m /work/aes_cipher_top/aes_cipher_top /work/aes_cipher_top/aes_cipher_top

Step - 4: "fix rtl" performs RTL optimizations.

mantle[5]:> fix rtl $m
mantle[5]:> fix rtl $m ################### Starting Standard fix rtl #################### MSG-10   While running 'run rtl expression /work/aes_cipher_top/aes_cipher_top': EXP-4    Labeling datapath cells EXP-5    Grouping datapath cells into expression models EXP-6    Flattening expressions for expression models EXP-7    Resource sharing over flat expressions EXP-8    Generating DPF for expression models CMD-8    cputime  0.4 minutes, walltime  0.4 minutes, process memory  133.4 MB, peak memory          144.4 MB, command "run rtl implement /work/aes_cipher_top/aes_cipher_top" MSG-10   While running 'export verilog equation /work/aes_cipher_top/aes_cipher_top          snap/aes_cipher_top%fix-rtl-final%vereqn.veq': WRI-2    Writing file snap/aes_cipher_top%fix-rtl-final%vereqn.veq. MSG-10   While running 'export volcano snap/aes_cipher_top%fix-rtl-final.volcano': LAVA-26  Writing library /cl013lv LAVA-26  Writing library /work LAVA-26  Writing library /macro_lib LAVA-900 Successfully froze lava into volcano snap/aes_cipher_top%fix-rtl-final.volcano:            1 seconds,    1 on cpu. LAVA-248 Volcano file size: 55.8 MByte, data compression was not used. LAVA-251 Data throughput 44.352 MB/s (1.26 s elapsed) ################### Finished Standard fix rtl #################### CMD-8    cputime  0.4 minutes, walltime  0.4 minutes, process memory  133.4 MB, peak memory          144.4 MB, command "fix rtl /work/aes_cipher_top/aes_cipher_top"

Step - 5: "fix netlist" performs the logical optimizations.

mantle[5]:> fix netlist $m $l

Step - 6: "export verilog netlist" saves the verilog netlist file to specified file name for example "filename_netlist.v". The proper usage of export command is shown below.

mantle[6]:> export verilog netlist $m aes_cipher_top_netlist.v

mantle[6]:>export verilog netlist $m aes_cipher_top_netlist.v MSG-10   While running 'export verilog netlist /work/aes_cipher_top/aes_cipher_top          aes_cipher_top_netlist.v': WRI-2    Writing file aes_cipher_top_netlist.v.

Note: The Netlist to GDSII flow will start from next point. You can import any netlist file to the magma flow.

Step - 7: "run bind logical" will bind the unbound cells to the target library.

mantle[7]:> run bind logical $m $l
mantle[7]:>run bind logical $m $l MSG-10   While running 'run bind logical /work/aes_cipher_top/aes_cipher_top /cl013lv': BND-3    Binding model /work/aes_cipher_top/aes_cipher_top to library /cl013lv BND-4    All cells bound in model /work/aes_cipher_top/aes_cipher_top

Step - 8: "report model" Checks the model for basic netlist and floorplan integrity (for example, cell overlap and dangling input pins, etc.,).

mantle[8]:> report model $m

mantle[8]:>report model $m MSG-10   While running 'report model /work/aes_cipher_top/aes_cipher_top': CK-5 Collecting data on model aes_cipher_top ..... ------------------- M O D E L  S T A T I S T I C S ------------------ Generated for user temp on host vlsi2             on Thu Mar  1 13:30:20 2007 Model: /work/aes_cipher_top/aes_cipher_top Cell Statistics                - count -    - area -         - legend -   Super cells:                      12402      0.174mm2         (s)   Bound cells:                         24      (without layout data)   Constant cells:                     524   Total cells:                      12950      0.174mm2 Net Statistics   Number of signal nets:         13815   Number of power/clock nets:        0   Number of cell pins:           50077   Average pins per signal net:    3.70       (maximum = 1668) Dangling Pin Statistics   Dangling cell pins:              276       (0 dangling input pins)   Dangling model pins:              14     Estimated signal wire length:   7.653       meter CK-16    Use 'check model /work/aes_cipher_top/aes_cipher_top' to check its sanity. ---------------------------------------------------------------------   force timing clock {/work/aes_cipher_top/aes_cipher_top/mpin:clk}

NEXT---->>>>>Import Design Constraints

The Magma RTL to GDSII using command prompt- Part 1

The detailed flow is explained in the three stages as follows:

Stage 1: Invoking Mantle, Import RTL Design and Imoport Design Constraints

Invoking Mantle

Step - 1: Create a directory where you want put all your magma synthesis documents. In this example, aes is the working directory.

bash-2.05b$ mkdir aes

This will create a directory called "aes" . Copy your all RTL Code in to the created directory. Then go to the directory to invoke the magma tool.

bash-2.05b$ cd aes

Step - 2: Invoke the mantle using the path "/magma/2004_12_29.0014/linux24_x86_64/bin/mantle". Mantle is the command prompt of the Magma Blast Fusion Tool.

bash-2.05b$ /magma/2004_12_29.0014/linux24_x86_64/bin/mantle

MEM-4    WARNING: Unusually large stacksize of 17592186044416.0MB reserved by          user's shell resource limits. This may inhibit utilization of all          available system memory resources.  Recommended is 8000k Copyright (C) 1997-2004 Magma Design Automation Inc. mantle version 4.1.57-linux24_x86_64 (compiled Dec 28 2004 23:43:34) LIC-1    Setting default license file to          '/magma/2004_12_29.0014/common/license'. LIC-12   The following features have been checked out: BLAST_VIEW BLAST_WRAP          BLAST_SPEED BLAST_BUILDER BLAST_PLAN BLAST_RTL BLAST_LOGIC BLAST_SI          BLAST_RAIL OSD-100  Running /magma/2004_12_29.0014/linux24_x86_64/bin/mantle on host          "vlsi2" with pid 30575 for user "temp" started on Thu Mar 01          01:18:55 PM IST 2007 in directory /home/temp/noors/aes mantle[1]>

Note: If you have any problem in opening the mantle please contact to CS623 TAs. If you come across any error stating Error UI-39 in invoking the tool ask System Administrator to run "nscd" demon. If you come across any license related problems, then use "export LM_LICENSE_FILE=2700@10.6.5.27" at your command prompt. Still if you have any problem please contact System Administrator.

Directory Structure Generated by Magma

Files generated by Magma: You can also review the contents of two automatically-generated directories. The logfiles directory contains logs of the sessions you run, and the snap directory contains volcanos and reports of design statistics that reflect the design at the end of each part of the flow.

Logfiles Directory: When you start the tool, a file called mantle.log is created. This file is usually the most useful file in the logfiles directory. It contains a full record of your latest session. With each new session you start, the file is renamed to mantle#.log (# is a number) and the mantle.log file is overwritten with the latest information. In the tool, to find where the file has been saved, use the query logfile command.

Snap Directory: The snap directory is created locally in the directory where you have started the tool. This directory stores snapshot volcanos and status reports that show design statistics during the flow. Use a text editor to review the snapshot reports or use a snapshot volcano to rerun the flow from a specific step. There are several config, query and report commands related to snap, which are identified in the man pages.

Step - 3: To invoke the Graphical User Interface (GUI) use the following command.

mantle[1]> ui start

The above command will opens the GUI based work space of the Magma Blast Fusion.

Importing the Library Volcano

To use the provided design library, import the library and technology rules together in the form of a Volcano. A Volcano is a Magma database that stores design information.

Step - 4: Import the library using the following command where all the logic cells are stored. (Please verify the library path with course TA). In this example we are using the Magma 130nm library cell for synthesis. Import volcano command reads the data model from a disk.

mantle[0]:> import volcano /magma/cl013lv.volcano

mantle[0]:>import volcano /magma/cl013lv.volcano MSG-10   While running 'import volcano /magma/cl013lv.volcano': LAVA-333 This volcano erupted Tue Jan 21 12:42:38 2003 EST for user jwalston (Joe Walston)          (v14c1) LAVA-24  'import volcano' importing global config settings from volcano, existing settings          maybe overwritten LAVA-27  Reading library /cl013lv LAVA-874 All cells were bound as a result of this 'import volcano'. LAVA-902 Melted back from volcano '/magma/cl013lv.volcano' (   2 seconds elapsed of which            2 on CPU). LAVA-249 Volcano file size: 34.6 MByte (57.1 MB data, Compression = 1.65x) LAVA-251 Data throughput 21.631 MB/s (2.64 s elapsed)

"Set l " set the variable for library name. The library name that we are using is cl013lv.

mantle[0]:>set l /cl013l
mantle[0]:>set l /cl013lv /cl013lv

Next ---->>>>Import the RTL Design