Import the RTL Design

Import the RTL Design 


Step - 1: Now import your RTL code in a sequence of top module file is followed by the rest of the design files. For purpose of clear explanation here we are using a standard AES design. It is designed using verilog and whose topmodule name is "aes_cipher_top". AES design contains the following verilog files.

aes_cipher_top.v (Top Module)
aes_sbox.v
aes_rcon.v
aes_key_expand_128.v

Step - 2: "import rtl" reads the RTL files. To analyze RTL code use "-analyze" at the end. "-analyze" is optional command.

mantle[0]:> import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v aes_key_expand_128.v

mantle[0]:>import rtl aes_cipher_top.v  aes_sbox.v aes_rcon.v aes_key_expand_128.v MSG-10   While running 'import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v          aes_key_expand_128.v': RTL-3    Building model aes_cipher_top(aes_cipher_top) RTL-3    Building model aes_key_expand_128(aes_key_expand_128) RTL-3    Building model aes_sbox(aes_sbox) RTL-3    Building model aes_rcon(aes_rcon) /work/aes_cipher_top/aes_cipher_top

Step - 3: "set m" set the variable for the top level Design. In this design the top level model is "/work/aes_cipher_top/aes_cipher_top". The top level model path is displayed at the end of the report of the "import rtl" command.

mantle[0]:>set m /work/aes_cipher_top/aes_cipher_top

mantle[4]:>set m /work/aes_cipher_top/aes_cipher_top /work/aes_cipher_top/aes_cipher_top

Step - 4: "fix rtl" performs RTL optimizations.

mantle[5]:> fix rtl $m
mantle[5]:> fix rtl $m ################### Starting Standard fix rtl #################### MSG-10   While running 'run rtl expression /work/aes_cipher_top/aes_cipher_top': EXP-4    Labeling datapath cells EXP-5    Grouping datapath cells into expression models EXP-6    Flattening expressions for expression models EXP-7    Resource sharing over flat expressions EXP-8    Generating DPF for expression models CMD-8    cputime  0.4 minutes, walltime  0.4 minutes, process memory  133.4 MB, peak memory          144.4 MB, command "run rtl implement /work/aes_cipher_top/aes_cipher_top" MSG-10   While running 'export verilog equation /work/aes_cipher_top/aes_cipher_top          snap/aes_cipher_top%fix-rtl-final%vereqn.veq': WRI-2    Writing file snap/aes_cipher_top%fix-rtl-final%vereqn.veq. MSG-10   While running 'export volcano snap/aes_cipher_top%fix-rtl-final.volcano': LAVA-26  Writing library /cl013lv LAVA-26  Writing library /work LAVA-26  Writing library /macro_lib LAVA-900 Successfully froze lava into volcano snap/aes_cipher_top%fix-rtl-final.volcano:            1 seconds,    1 on cpu. LAVA-248 Volcano file size: 55.8 MByte, data compression was not used. LAVA-251 Data throughput 44.352 MB/s (1.26 s elapsed) ################### Finished Standard fix rtl #################### CMD-8    cputime  0.4 minutes, walltime  0.4 minutes, process memory  133.4 MB, peak memory          144.4 MB, command "fix rtl /work/aes_cipher_top/aes_cipher_top"

Step - 5: "fix netlist" performs the logical optimizations.

mantle[5]:> fix netlist $m $l

Step - 6: "export verilog netlist" saves the verilog netlist file to specified file name for example "filename_netlist.v". The proper usage of export command is shown below.

mantle[6]:> export verilog netlist $m aes_cipher_top_netlist.v

mantle[6]:>export verilog netlist $m aes_cipher_top_netlist.v MSG-10   While running 'export verilog netlist /work/aes_cipher_top/aes_cipher_top          aes_cipher_top_netlist.v': WRI-2    Writing file aes_cipher_top_netlist.v.

Note: The Netlist to GDSII flow will start from next point. You can import any netlist file to the magma flow.

Step - 7: "run bind logical" will bind the unbound cells to the target library.

mantle[7]:> run bind logical $m $l
mantle[7]:>run bind logical $m $l MSG-10   While running 'run bind logical /work/aes_cipher_top/aes_cipher_top /cl013lv': BND-3    Binding model /work/aes_cipher_top/aes_cipher_top to library /cl013lv BND-4    All cells bound in model /work/aes_cipher_top/aes_cipher_top

Step - 8: "report model" Checks the model for basic netlist and floorplan integrity (for example, cell overlap and dangling input pins, etc.,).

mantle[8]:> report model $m

mantle[8]:>report model $m MSG-10   While running 'report model /work/aes_cipher_top/aes_cipher_top': CK-5 Collecting data on model aes_cipher_top ..... ------------------- M O D E L  S T A T I S T I C S ------------------ Generated for user temp on host vlsi2             on Thu Mar  1 13:30:20 2007 Model: /work/aes_cipher_top/aes_cipher_top Cell Statistics                - count -    - area -         - legend -   Super cells:                      12402      0.174mm2         (s)   Bound cells:                         24      (without layout data)   Constant cells:                     524   Total cells:                      12950      0.174mm2 Net Statistics   Number of signal nets:         13815   Number of power/clock nets:        0   Number of cell pins:           50077   Average pins per signal net:    3.70       (maximum = 1668) Dangling Pin Statistics   Dangling cell pins:              276       (0 dangling input pins)   Dangling model pins:              14     Estimated signal wire length:   7.653       meter CK-16    Use 'check model /work/aes_cipher_top/aes_cipher_top' to check its sanity. ---------------------------------------------------------------------   force timing clock {/work/aes_cipher_top/aes_cipher_top/mpin:clk}

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