Import Design Constraints

Import Design Constraints

Import the design constraints to review a timing check and timing report to make sure the constraints are complete and to establish a timing baseline for later comparison.

Step - 1: "force timing clock" will assign the timing constraint to the clock. To estimate the Worst late slack assign the clock period, rise and fall times of the clock. In this design example we are assigning the clock period as 1000ns (1 MHz clock) and, rise and fall times are 5ns and 10ns respectively.

Note: This command is used only in case of sequential circuits. (This command is not required in case of combinational circuit ). In general the combinational ciruit will have the +INF worst late slack.

mantle[1]:> force timing clock {/work/aes_cipher_top/aes_cipher_top/mpin:clk} 1000n -waveform {-rise 5n -fall 10n}

Step - 2: "report force timing" will report the timing summary for the forced or defined clock signal.

mantle[2]:> report force timing $m

mantle[12]:>report force timing $m ########################################### # Mantle analysis report # Command: #          report force timing \ #               /work/aes_cipher_top/aes_cipher_top # Date:    Thu Mar  1 13:37:43 2007 # Version: mantle version 4.1.57-linux24_x86_64 ###########################################   force timing clock {clk} 1000000p -waveform { -rise 5000p -fall 10000p}  -context /work/aes_cipher_top/aes_cipher_top

Step - 3: "force wire model" will defines the design wire model to either constant or wireload model. In this design example we are defining the wire model as a constant model using the following command.

mantle[3]:> force wire model constant $m

Step - 4: "report timing summary" will generates a timing analysis summary report for the model.

mantle[4]:> report timing summary $m

mantle[4]:>report timing summary $m ############################################## # Mantle analysis report # Command: #          report timing summary \ #               /work/aes_cipher_top/aes_cipher_top # Date:    Thu Mar  1 13:39:07 2007 # Version: mantle version 4.1.57-linux24_x86_64 ##############################################     Cell count         12926  Node count         50466  Event count        98800  Endpoint count      1180                             Worst late slack    4248  Failing endpoints      0    For more information, try these commands:              "report timing path"                       "report timing check"                       "report timing detail"

Note: In general, check the timing summary report and find what is value of Worst Late Slack. If it is positive with small integer then proceed to next step (try to make the worst late slack as either 0 or 1). If the worst late slack is negative then make it positive by varying the timing information that is defined for the clock (Period, Rise and Fall times). Do this until you get the positive slack (0 is preferred). Make the iterative run of the previous three commands to get the positive slack of significant amount. The following report will give the idea of how to achieve the significant positive slack.

Step - 5: "check timing" will Checks and reports on the completeness of the timing constraints.

mantle[5]:> check timing $m

mantle[5]:>check timing $m Checking Timing of Model /work/aes_cipher_top/aes_cipher_top Use the -detail switch for more information.   Checking for missing cell models   0 leaf cells have no timing model. 0 cells are hierarchical, but contain no submodels.   Checking clock properties   0 clocks have non-unate distribution networks. 0 clocks had multiple clock sources without multiple clock propagation enabled. 0 clock end points were undriven. 1 nodes are nonvirtual clocks, but do not have latency specified.   Checking for unconstrained I/O   There are 258 unconstrained inputs. There are 129 unconstrained outputs.   Checking force consistency   0 nodes had both arrival and delay -to forces. 0 nodes had both required time and a check arc.   Checking for unconstrained timing nodes.   A total of 98800 timing events are found on 50466 nodes. 0 nodes have no timing information (i.e. zero events) and have no predecessors 0 more nodes have no timing information (i.e. zero events) 0 more nodes have infinite slack and no predecessors 308 more nodes have infinite slack and no successors 151 more nodes have infinite slack 934 nodes have events and times, but only from the default phase 1101 nodes are constants. 0 nodes are connected to power/ground.

Step - 6: "data flatten" will flattens the hierarchy under a model or cell.

mantle[6]:> data flatten $m

Step - 7: "run gate sweep" will Successively eliminates all unreachable cells, single-input cells, and constant cells from the design.

mantle[7]:> run gate sweep $m

mantle[6]:>data flatten $m MSG-10   While running 'data flatten /work/aes_cipher_top/aes_cipher_top': FLT-1    Flattening model: /work/aes_cipher_top/aes_cipher_top   mantle[7]:>run gate sweep $m MSG-10   While running 'run gate sweep /work/aes_cipher_top/aes_cipher_top': SWP-1    sweep changed 562 cells in /work/aes_cipher_top/aes_cipher_top.

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